1. Field of the Invention
The present invention relates to a testing circuit, and more particularly, it relates to a scan path forming circuit which is provided around a logic circuit provided in a semiconductor device for testing the same.
2. Description of the Background Art
In general, a design of providing a test simplifying circuit has been applied to a semiconductor device, for an operation test of a logic circuit which is provided in the semiconductor device.
Before explaining a scan test by the test simplifying design, a data circuit which is a logic circuit and input/output operations of the data circuit are now described with reference to FIG. 30.
FIG. 30 is a circuit diagram showing a data circuit 1 and circuits for inputting and outputting data in and from the data circuit 1.
Throughout the specification, symbols denote data or signals and terminals in common. For example, symbol IN0! may denote input data or a data input terminal.
The data circuit 1 is now described. The data circuit 1 comprises input terminals DI0! to DI3! and output terminals DO0! to DO3!. This data circuit 1 is a circuit outputting output data DO0! to DO3!, which are specific to input data DI0! to DI3! supplied to the input terminals DI0! to DI3!, from the output terminals DO0! to DO3!. The data circuit 1 can be a combinational circuit or a memory circuit such as a RAM (random access memory). Data input terminals IN0! to IN3! and data output terminals OUT0! to OUT3! are connected to the input terminals DI0! to DI3! and the output terminals DO0! to DO3! through selectors 1020! to 1023! and flip-flops 40! to 43! described later respectively. Numbers! which are added to the data or terminals express bit numbers of data. As described above, the data inputted in or outputted from the terminals are associated with each other by bit numbers respectively. Therefore, the bit numbers are hereinafter omitted when the data or terminals are generically called or no variation with the bit numbers may be taken into consideration. Also when the bit numbers are omitted, the respective data correspond to the terminals of the respective bit numbers.
The circuits which are related to data input/output are now described. The selectors 102 and the flip-flops 4 are inserted between the input terminals DI of the data circuit 1 and the data input terminals IN and between the output terminals DO and the data output terminals OUT respectively, in order to hold input or output data. All selectors 102 are simultaneously controlled by a holding control signal HLD0 which is inputted from a holding terminal HLD0. The flip-flops are D flip-flops, or flip-flops having functions which are similar to those of D flip-flops. Functions of the selectors 102 and the flip-flops 4 are similar in every bit number, and identical to each other on the input and output sides. While the following description is made on the selectors 102 and the flip-flops 4 provided on the input side, this also applies to the output side.
The state of connection is now described. Each selector 102 comprises two data input terminals, i.e., a data input 0 terminal which is selected and connected when the holding control signal HLD0 is "0" and a data input 1 terminal which is selected and connected when the holding control signal HLD0 is "1". The data input 0 terminal is connected with each data input terminal IN, while the data input 1 terminal is connected with an output terminal of the flip-flop 4. An output terminal of each selector 102 is connected to an input terminal of each flip-flop 4. The output terminal of the flip-flop 4 is connected to each input terminal DI and the data input 1 terminal of the selector 102 in common.
Circuit operations in the aforementioned state of connection are now described. When the holding control signal HLD0 is "0", data which are inputted in the data input 0 terminals of the selectors 102 are connected to the output terminals of the selectors 102. Therefore, input data IN are supplied to the input terminals DI through the selectors 102 and the flip-flops 4. When the holding control signal HLD0 is "1", on the other hand, the data input 1 terminals are selected, whereby data outputted from the output terminals of the flip-flops 4 are supplied to the input terminals of the flip-flops 4 through the selectors 102. Thus, the data of the flip-flops 4 are held.
The circuit operations in the circuits shown in FIG. 30 are summarized with respect to the input and output sides as follows: When the holding control signal HLD0 is "0", the input data IN are inputted in the input terminals DI, and output data DO are outputted from the data output terminals OUT. Namely, the input operation and the output operation are synchronized with each other. When the holding control signal HLD0 is "1", on the other hand, the input data DI and the output data DO are held by the selectors 102 and the flip-flops 4 respectively.
The scan test is now described.
The scan test is adapted to:
1. provide a scan path on the circuit to be tested,
2. supply test patterns from the scan path to the circuit,
3. incorporate output data outputted from the circuit with respect to the test patterns in the scan path again, and
4. analyze the results.
The scan test is a technique of a test simplifying design. The scan path is implemented by converting flip-flops which are connected to input or output terminals of the tested circuit to scan flip-flops.
FIG. 31 is a circuit diagram showing a state of converting a flip-flop 4 to a scan flip-flop SFF. In this case, scan conversion is adapted to connect a selector 103 to an input terminal of the flip-flop 4. An output of the selector 103 is switched by a shift mode signal SM. Data D and scan-in data SI are inputted in a data input 0 terminal and a data input 1 terminal of the selector 103 respectively. The data D is selected when the shift mode signal SM is "0", while the scan-in data SI is selected when the signal SM is "1", to be inputted in the flip-flop 4.
FIG. 32 is a circuit diagram showing a data circuit 1 which is provided with a scan path. Connection circuits PCC0! to PCC3! consisting of selectors 102 and 103 and flip-flops 4 are connected between data input terminals IN0! to IN3! and input terminals DI0! to DI3! respectively on the input side. Similarly, connection circuits PCC0! to PCC3! are connected between data output terminals DO0! to DO3! and output terminals OUT0! to OUT3! respectively on the output side. FIG. 33 shows each connection circuit PCC.
The functions of the connection circuits PCC provided on the input and output sides are identical to each other, and hence description is made on the state of connection of the connection circuit PCC shown in FIG. 33 with reference to the input side, similarly to FIG. 30.
The selector 102 has a data input 0 terminal which is connected with a data input terminal IN, and a data input 1 terminal which is connected with an output terminal of the flip-flop 4. An output terminal of the selector 102 is connected to a data input 0 terminal of the selector 103. A data input 1 terminal of the selector 103 is connected with a scan-in terminal SI. An output terminal of the selector 103 is connected to an input terminal of the flip-flop 4, while output data of the flip-flop 4 is inputted in the data input 1 terminal of the selector 102 as described above, and further outputted as scan-out data SO of the connection circuit PCC or serial input data Q.
As shown in FIG. 32, each scan-out data SO defines scan-in data SI of a connection circuit PCC having the next bit number, and is inputted to the shift-in terminal SI of the connection circuit PCC. The scan-out data SO of the input side connection circuit PCC3! defines the scan-in data SI of the output side connection circuit PCC0!, and the scan-out data SO of the output side connection circuit PCC3! is outputted as the scan-out data SO of the overall scan path.
The circuit operations are now described. The operations of the circuits shown in FIG. 32 include an ordinary operation and a scan test operation.
The ordinary operation is first described. The ordinary operation of the circuits shown in FIG. 32 is similar to the operation of the circuits shown in FIG. 30.
In the ordinary operation, the shift mode control signal SM is set at "0". At this time, input data IN are incorporated in the input terminals DI of the data circuit 1 through the connection circuits PCC on the input side if a holding control signal HLD0 is "0". On the other hand, output data DO are outputted from the data output terminals OUT through the connection circuits PCC on the output side. If the holding control signal HLD0 is "1", on the other hand, the input and output data IN and DO are held in the connection circuits PCC respectively.
The scan test operation is now described. In the scan test, shift-in of test patterns, execution, and shift-out of test results are successively performed.
1. Shift-In of Test Patterns
In preparation for inputting of test patterns in the data circuit 1, the test patterns are shifted in the input side connection circuits PCC. When the shift mode control signal SM is set at "1", the shift patterns to be inputted in the data circuit 1 can be shifted in from the scan-in terminal SI. The data circuit 1 of this prior art is of four bits, and hence 4-bit test patterns are shifted in the connection circuits PCC. The test patterns are shifted in the following order of the input side connection circuits PCC0!.fwdarw.PCC1!.fwdarw.PCC2!.fwdarw.PCC3!, to be inputted in the input side connection circuits PCC0! to PCC3!.
2. Execution
The shift mode control signal SM is set at "0". If the holding control signal HLD0 is "1", data after completion of the test pattern shift-in, i.e., the test patterns, are held in the input side connection circuits PCC, while data after completion of the test pattern shift-in are held in the output side connection circuits PCC. If the holding control signal HLD0 is "0" when the shift mode control signal SM is set at "0", the input data IN are incorporated in the input terminals DI, and the output data DO which are the test results of the data circuit 1 are outputted from the data output terminals OUT. When the holding control signal HLD0 is thereafter converted from "0" to "1", the input data IN are held in the input side connection circuits PCC while the output data DO which are the test results are held in the output side connection circuits PCC.
3. Shift-Out of Test Results
The shift mode control signal SM is set at "1". At this time, the test results are successively shifted out from the scan-out terminals SO.
The above are the circuit operations of the circuits shown in FIG. 32.
As shown in FIG. 32, two selectors 102 and 103 are included between each data input terminal IN for the ordinary operation and each input terminal DI of the data circuit 1. Similarly, two selectors 102 and 103 are included between each output terminal DO of the data circuit 1 and each data output terminal OUT for the ordinary operation. Therefore, set-up is increased and the circuit speed in the ordinary operation is disadvantageously reduced.